Nanotechnology broadly encompasses materials and devices whose functional dimensions are in nanometers, as well as the bottom-up techniques of manufacturing such materials and devices. The new materials include, for example, carbon nanotubes and semiconducting nanowires. Nanotechnology is viewed by many as being the most promising area of research aimed at overcoming the physical constraints that have hampered development of devices (e.g., computer memory cells) smaller than the current micrometer-sized ones now widely available. Nanotechnology may hold the promise of redirecting the technology road map for CMOS based VLSI design and creating new trends in computer architecture.
A fundamental challenge remains, however, regarding how to interface nanometer-sized components to present micrometer sized devices. Difficulties arise in achieving a satisfactory interface not only because of the scale mismatch, but also because conventional device techniques are based on miniaturizing a precise interconnect and device geometry (top down), while at the nanometer scale designers have to cope with less precise geometry and/or location of components.
These difficulties are seen, for example, in U.S. Pat. No. 6,128,214 (the '214 patent) and U.S. Pat. No. 6,256,767 (the '767 patent), both to Kuekes, et al., which disclose a molecular wire crossbar memory (MWCM) and a demultiplexer for a molecular wire crossbar network (MWCN DEMUX), respectively. The MWCM disclosed by Kuekes, et al. is a conventional listing type memory, albeit, at a nanoscale, utilizing an array of nanometer-sized conducting and semiconducting wires (“nanowires”). The demultiplexer disclosed by Kuekes, et al. is a MWCN DEMUX utilizing a two-dimensional array of nanometer-sized switches, each of which comprises a pair of crossed wires forming a junction and a least one “connector species” comprising a bi-stable molecule.
One apparent difficulty with a MWCM is that a direct, one-to-one connection of its nanometer-sized input and output buses to a micrometer-sized component would likely consume more area on a chip than the MWCM itself, thus possibly undercutting the very advantage of the nanometer-sized component. The MWCN DEMUX address this problem by lithographically connecting micrometer-sized wire to the MWCM nanometer-sized input and output wires. Currently available lithography techniques, however, can make unique addressing of each nanowire problematic. One possible solution is searching the address space of the demultiplexer to determine the addresses that uniquely correspond to each nanowire. Such an approach for a device comprising M microwires and N nanowires, however, requires M×N searches, which typically results in a large number of searches being performed. Moreover, once the addresses are determined, they typically must be stored in micrometer-sized circuitry external to the MWCM.